Electronic systems such as transceivers use dock and data recovery (CDR) circuits to acquire and track incoming signals. An incoming signal may include a preamble code that includes a relatively easily identifiable binary code sequence that precedes an information packet. More specifically, receipt of the preamble typically precedes receipt of a sync message that proceeds an information packet. In an electronic system that uses a packet based protocol, for example, each packet typically is preceded by a preamble that contains a sequence of binary logic values of a predetermined number which alternate at a predetermined clock interval.
In a wireless communication system, a receiver receives RF information signal to convert it to a digital data stream. During receipt of an information signal, additive white Gaussian noise often superimposes upon the received signal and distorts it either in constructive or destructive fashion. FIG. 1A is an illustrative example demodulated input signal timing diagram showing a portion of modulated information input signal and superimposed noise. FIG. 1B is an illustrative example corresponding demodulated signal showing both zero crossing noise edges and zero crossing information input signal edges. During first and third time intervals, T1, T3, only noise is received. During a second time interval T2 a preamble portion of an information input signal having values 1, 0, 1, 0, 1, 0, 1, 0, is received amidst the noise.
At a reasonable received signal power level a preamble signal sequence within a received information signal has well defined zero crossing edges having time period equal to data rate of the receiver is configured to receive. The example received preamble like information signal has zero crossings that are spaced apart by 1/data rate, for example. A CDR circuit can exploit the zero crossing edges of an incoming preamble sequence to align a locally generated dock signal to the incoming packet data stream. Often, a CDR circuit uses an oversampled digital phase locked loop (DPLL) operated at a clock frequency much higher than a target data rate to detect preamble packet signal edges to detect the presence of an incoming packet. A clock and data recovery system may be configured to extract demodulated dock and data information from a data stream that is modulated by various schemes such as frequency shift keying (FSK) and to cause a numerically controlled oscillator (NCO) to generate a recovered clock.
In general, a receiver spends much of its time waiting to receive packet data. During that wait time, the receiver ordinarily receives random white Gaussian noise with zero mean. The received noise typically has far more frequent zero crossing edges at a demodulator output than does an information signal, and the time between consecutive noise edges is variable and random. However, noise can from time to time have characteristics of a preamble signal at a demodulator output, which can result in false packet data detection.